Saturday, February 26, 2011

AMD shares more on Bulldozer at ISSCC

At ISSCC we’ll be covering new details throughout the week. For example: The Bulldozer core circuit design is described in detail in ISSCC paper (Session 4.5) titled “Design Solutions for the Bulldozer 32nm SOI 2-core processor module in an 8-core CPU” ( This paper describes design techniques used to wring maximum performance from the GLOBALFOUNDRIES 32nm SOI manufacturing process. Changes in clocking, latching, power management and on-chip memories are part of the comprehensive circuit updates incorporated into Bulldozer. These are detailed in the paper, along with significant power reduction improvements, including clock gating, a new low-power flop design, and L1 cache power improvements.

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via AMD

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